1. Field of the Invention
The present invention relates to a topology for a system of transmission lines for delivering a clock signal from one terminal to other terminals with an equal phase delay.
2. Description of the Related Art
FIG. 1 shows a topology for a standard clock tree. In FIG. 1, a signal is provided to the clock tree at a single terminal 100. The clock tree then distributes the signal to four terminals 101-104 over equal line lengths to achieve equal phase delays. The standard clock tree is made up of units composed of six line segments 111-116 in the shape of the letter xe2x80x9cHxe2x80x9d as shown in FIG. 1. Multiple xe2x80x9cHxe2x80x9d shaped units may be linked together to form a clock tree for distributing a clock signal to more terminals as shown in FIG. 2. Using the xe2x80x9cHxe2x80x9d shaped units to form a clock tree, a single clock signal can be distributed to 4N terminals with an equal phase delay, wherein N is an integer.
Clock trees are useful in devices such as field programmable gate arrays (FPGAs). FIG. 3 shows a block diagram illustrating components of a typical FPGA. As shown, the typical FPGA includes input/output buffers (IOBs), an array of configurable logic blocks (CLBs), and routing resources. The I/O buffers are arranged around the perimeter of the device and provide an interface between internal components of the FPGA and external package pins. The routing resources include signal lines and other components such as multiplexers for interconnecting the I/O buffers and CLBs.
Each CLB includes a series of look up tables. Each look up table in a CLB includes a number of memory cells and a decoder. Inputs to a look up table are decoded by the decoder to select one of the memory cells for connecting to its output. The memory cells can be programmed so that the look up table can be configured to operate as an AND gate, OR gate, or other gate providing a Boolean function. Each look up table typically has three or four inputs provided from routing resources of the FPGA, and a single output line provided to the routing resources of the FPGA.
The output of each look up table can be registered and receive a common clock signal to enable synchronous operation with other look up tables, either in the same CLB or other CLBs. Because look up tables in different CLBs may be located a significant distance apart, a single clock signal line driving the registers of both look up tables will experience a significant phase delay between the look up tables preventing synchronous operation.
To prevent phase delays and provide synchronous operation in a FPGA, a clock signal is typically distributed to the CLBs using a clock tree as shown in FIG. 1 or FIG. 2. Output terminals of the clock tree such as 101-104 are each provided to a separate CLB or an IOB. With a clock tree made up of xe2x80x9cHxe2x80x9d shaped units as shown in FIGS. 1 or 2, the number of destinations which can be supported is 44.
The present invention provides a clock tree topology which will support a number other than 4N destinations.
Referring to FIG. 4, the clock tree topology of the present invention includes a single input terminal 400 and distributes the clock signal to three terminals 421-423 with an equal phase delay. The topology includes four lines 401-404 connected together at a connection node 450 with adjacent lines forming right angles. A second end of the line 404 forms the clock signal input terminal 400. A second end of the remaining lines 401-403 are connected to first ends of lines 411-413. Second ends of the lines 411-413 form the terminals 421-423 which may be connected to CLBs. A right angle is formed between each of the lines 401-403 and the respective one of the lines 411-413 to which it connects.
To optionally connect to other numbers of CLBs than can be done with the topology of FIG. 4, the present invention further includes a combination of the structure of FIG. 4 with the xe2x80x9cHxe2x80x9d type structure of FIG. 1 to form the clock tree topology shown in FIG. 6.